ISL-4800 High-Speed Serial - MIPI/SMIA/LVDS

The ISL-4800 supports multiple high-speed serial interface standards (MIPI® and SMIA) and provides 25 additional high-speed serial LVDS line pairs that can be used to interface to non-standard high-speed serial interfaces.

The ISL-4800 high-speed serial interface also supports both DVI and HDMI digital video standards. 


MIPI ® (Mobile Industry Processor Interface) is an industry consortium, which defines standards for the interface between modules of a mobile device. Two of those standards are DPHY, defining the physical level of high speed communication, and CSI2, defining the Camera Serial Interface.

 The ISL-4800 CSI2 mode functionality includes:

  • 1, 2, or 4 configurable data lanes
  • Up to 960 Mbps per lane
  • Interface signals as defined in Appendix B of MIPI ® CSI2 specifications
  • Support of all primary data formats, and more

The IP core used in the ISL-4800 has passed the UNH IOL labs interoperability tests and has been qualified to 960 Mbps per data lane.
The hardware supports a single clock lane and up to four data lanes of MIPI compliant LVDS pairs. The FPGA core logic supports only two data lanes by default, with a future option to support four data lanes.


SMIA (Standard Mobile Imaging Architecture) is an industry consortium, which defines standards for mobile imager modules. SMIA standards encompass several aspects of the imager, allowing pin-level compatibility. One of those standards is CCP2 – high speed communication between the sensor and a host application processor.
The ISL-4800 supports the following CCP2 Mode functionality features:

  •  Classes 0, 1, and 2
  •  Up to 650 Mbps
  •  Supports all data formats as defined in Chapter 5 of the CCP2 Specification
  •  Receiver behavior as recommended in Chapter 8 of the CCP2 Specifications.


A total of twenty-four (24) LVDS pairs are provided in two functional/electrical groups; Bank-16 and Bank-18. Each bank is supported within separate FPGA I/O blocks with separate timing and electrical I/O references.